1. Field of the Invention
The present invention relates to a semiconductor device and a band gap reference power supply utilizing the same.
2. Description of the Background Art
In obtaining a reference voltage with high stability and small variation against temperature in a semiconductor integrated circuit, a circuit system called "band gap reference power supply" employing a bipolar transistor is often used. The band gap reference power supply circuit, which has been introduced by R. J. Widlar in 1971 ("New Developments in IC Voltage Regulators" R. J. Widlar, IEEE J. Solid-State Circuits, SC-6, 2-7 (February, 1971)) utilizes the physical characteristics of base-emitter voltage of a silicon transistor when biased in the forward direction as shown in FIGS. 8 and 9. In general, a temperature coefficient of the base-emitter voltage of a transistor is about -2 mV/.degree.C., and then the base-emitter voltage is about 1.2 V in absolute zero point, which is almost equal to a band gap voltage (energy gap, 1.12 V when Ta=300.degree. K). Adding a voltage proportional to the absolute temperature to the base-emitter voltage of the transistor makes an output voltage of the band gap reference power supply. It is possible to make the temperature coefficient almost zero by controlling the voltage to be added so that the output voltage should be 1.2 V, thereby obtaining an output voltage with extremely small temperature dependency. Such a system is called "band gap reference power supply".
[The First Background Art]
The band gap reference power supply using a bipolar structure obtains the required characteristics without extra technique. FIG. 8 illustrates the first background art of a basic circuit of the band gap reference power supply using the bipolar transistor. In general, the relation between a base-emitter voltage V.sub.BE and an emitter current I.sub.E is expressed as follows: ##EQU1## where K, T, g and I.sub.S represent Boltzman's constant, absolute temperature, electrical charge and reverse saturation current, respectively. In FIG. 8, when the emitter area ratio between the transistors Q1 and Q2 is 1:n, base-emitter voltages V.sub.BE1 and V.sub.BE2 of the transistors Q1 and Q2 are expressed by using emitter currents I.sub.E1, I.sub.E2 and a reverse saturation current I.sub.S1 of the transistor Q1 as follows: ##EQU2##
Assuming that voltages across resistors R1 and R2 are V.sub.R1 and V.sub.R2, respectively, the following relations are hold: EQU V.sub.R1 =V.sub.OUT -V.sub.BE1 =R1.multidot.I.sub.E1 EQU V.sub.R2 =V.sub.OUT -V.sub.BE3 =R2.multidot.I.sub.E2 ( 3)
When the base-emitter voltage V.sub.BE1 of the transistor Q1 is almost equal to a base-emitter voltage V.sub.BE3 of a transistor Q3 regardless of a base current, the following equation is obtained: EQU R1.multidot.I.sub.E1 =R2.multidot.V.sub.E2 ( 4)
Since a voltage V.sub.R3 across a resistor R3 is equal to a voltage difference .DELTA.V.sub.BE (=V.sub.BE1 -V.sub.BE2) between the base-emitter voltages of the transistors Q1 and Q2, the following relation is hold: ##EQU3##
Accordingly, the following equation is obtained: ##EQU4##
The first term of Formula (6) is proportional to the absolute temperature.
[The Second Background Art]
FIG. 9 illustrates a circuit configuration of the second background art of the band gap reference power supply. In FIG. 9, when the emitter area ratio between the transistors Q1 and Q2 is 1:n, the voltages V.sub.R1 and V.sub.R2 across the resistors R1 and R2 are expressed as follows: EQU V.sub.R1 =R1.multidot.I.sub.E1 =V.sub.OUT -V.sub.BE1 EQU V.sub.R2 =R2.multidot.I.sub.E2 =V.sub.OUT -(V.sub.BE2 +R3.multidot.I.sub.E3) (7)
The voltages V.sub.R1 and V.sub.R2 are an inverted input V(-) and a non-inverted input V(+), respectively, of an operational amplifier A1 (input means). Therefore, assuming that the amplification factor of the operational amplifier A1 is A.sub.v, the relation is expressed as follows: EQU V.sub.OUT =A.sub.v {V(+)-V(-)}=A.sub.v (R2.multidot.I.sub.E2 -R1.multidot.I.sub.E1) EQU .thrfore.R1.multidot.I.sub.E1 =A.sub.v (R2.multidot.I.sub.E2 -R1.multidot.I.sub.E2)-V.sub.BE1 ( 8)
The amplification factor A.sub.v is infinity (.infin.), and then the relation is expressed as follows: ##EQU5##
Accordingly, the following equation is obtained: ##EQU6##
The first term of Formula (10) is proportional to the absolute temperature.
In the background arts as mentioned above, the emitter area ratio 1:n between the transistors Q1 and Q2 as well as the resistances of the resistors R1, R2 and R3 are crucial determinants for the output voltage V.sub.OUT. Accordingly, it is an important task to achieve the emitter area ratio between the transistors Q1 and Q2 with high accuracy. The first and second background arts comprise a bipolar transistor Q1 and a bipolar transistor including n bipolar transistors Q21 to Q2n each having the same shape as the bipolar transistor Q1, connected in parallel with one another, as shown in FIG. 10, so that the area accuracy of each transistor should become higher. In FIG. 10, E1, B1 and C1 represent the emitter, base and collector of the transistor Q1, E21 to E2n, B21 to B2n and C21 to C2n represent the emitters, bases and collector terminals of the transistors Q21 to Q2n and W1 and W21 to W2n represent wells (island-shaped regions) which function as collector regions of the transistor Q1 and Q21 to Q2n, respectively.
FIG. 11 is a sectional view of a CMOS configuration which is an example of non-bipolar configuration. As shown in FIG. 11, the CMOS 5 comprises an N-channel MOS 6 and a P-channel MOS 7. When an n.sup.- -type semiconductor layer 1 is used as a substrate, the n.sup.- -type semiconductor layer 1, a p.sup.- -type diffused layer 2 which functions as a well and n.sup.+ -type diffused regions 3 to form a source (S) and a drain (D) are layered in the N-channel MOS 6. In the P-channel MOS 7, the n.sup.- -type semiconductor layer 1 and p.sup.+ -type diffused regions 8 to form a source (S) and a drain (D) are layered. The band gap reference power supply having the above configuration, as can be seen from the transistors Q1 and Q2 of FIG. 11, uses a parasitic transistor (artificial bipolar transistor) in which the n.sup.- -type semiconductor layer 1, the p.sup.- -type diffused layer 2 and the n.sup.+ -type diffused region 3 serve as collector, base and emitter, respectively. The triple-layered N-channel MOS 6 has an advantage in terms of manufacturing cost that the artificial bipolar transistors Q1 and Q2 of triple-layered configuration are formed simultaneously in a manufacturing process of the N-channel MOS 6. The configuration of FIG. 11 is used only for an emitter follower circuit since the n.sup.- -type semiconductor layer 1 is used as a collector in common.
In the first background art of FIG. 8, since the resistors R1 and R2 are disposed between the transistors Q1 and Q2, the transistors Q1 and Q2 do not have a common collector. Therefore the circuit of FIG. 8 cannot be of CMOS configuration but of bipolar configuration. On the other hand, in the second background art of FIG. 9, the transistors Q1 and Q2 have a common collector, so that the circuit of FIG. 9 can be of CMOS configuration as shown in FIG. 11 as well as of bipolar configuration.
In the circuit configurations shown in FIGS. 8 and 9, as clearly seen from the above Formulae, the accuracy in the voltage difference .DELTA.V.sub.BE between the base-emitter voltages of the transistors Q1 and Q2 is of extreme importance. In the first background art, the voltage difference .DELTA.V.sub.BE between the base-emitter voltages depends not only on the transistor characteristics but also the resistors R1 and R2, while in the second background art, it depends only on the transistor characteristics. In other words, in the second background art, controlling of the emitter areas of the transistors Q1 and Q2 has a significant effect on the whole circuit characteristics.
FIG. 12 is a plan view showing a layout of the CMOS 5 corresponding to the circuit diagram of FIG. 9. Reference signs E1 and E2 denote emitters of the transistors Q1 and Q2, respectively. Reference sign B denotes a common base of the transistors Q1 and Q2 which functions as a well and reference sign C denotes a common collector of the transistors Q1 and Q2 which functions a substrate. The area ratio between emitters E1 and E2 (emitter area ratio) is set to 1:n so as to obtain the predetermined base-emitter voltage difference .DELTA.V.sub.BE.
In the configuration of FIG. 11, the emitters E1 and E2 are the n.sup.+ -type diffused regions 3 and the areas thereof are determined only in diffusion process. It is very difficult to obtain a diffusion area with high accuracy and therefore there is high possibility of great error in its accuracy. As mentioned above, since the emitter area ratio has a significant effect on the electrical characteristics of the band gap reference power supply, the error in the emitter area ratio due to the error in diffusion area may cause a fatal flaw of the band gap reference power supply.
In general, when a well, a diffused region and the like are formed on a substrate, a stress is generated due to a difference of physical constant between the substrate and the well or between the well and the diffused region. The stress causes deflection in the substrate and thereby distortion is likely to occur in the shape of the diffused region located on the end portions. When emitters E1 and E2 are aligned transversely in a common well B as shown in FIG. 12, the emitter E1 of the transistor Q1 and the end portion of the emitter E2 of the transistor Q2 have distortion in their shape. In this case, the emitters E1 and E2 have the almost same distortion, and the distortion in area of the emitter E1 which is smaller is not negligible relatively to the area on design. Therefore, there is a possibility of bringing a great error in area ratio of the emitters E1 and E2. Thus, there is a problem that it is difficult to obtain a desired emitter area ratio (1:n) between the transistors Q1 and Q2 with high accuracy because of the area error of the emitter E1.